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Freescale Semiconductor
Document Number: MPC8308EC Rev. 1, 07/2010
MPC8308 PowerQUICC II Pro Processor Hardware Specification
This document provides an overview of the MPC8308 features and its hardware specifications, including a block diagram showing the major functional components. The MPC8308 is a cost-effective, low-power, highly integrated host processor. The MPC8308 extends the PowerQUICC family, adding higher CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. NOTE The information provided in this document is preliminary and is based on estimates only and refers to the pre-silicon phase, with no device characterization done. Freescale reserves the right to change the contents of this document as appropriate.
1
Overview
Figure 1 shows the major functional units within the MPC8308. The e300 core in the MPC8308, with its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the Power Architecture user instruction set architecture and provides hardware and software debugging
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25.
Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 2 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ethernet: Three-Speed Ethernet, MII Management . 15 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 24 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 43 Enhanced Secure Digital Host Controller (eSDHC) . 47 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 62 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 System Design Information . . . . . . . . . . . . . . . . . . . 81 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 85 Document Revision History . . . . . . . . . . . . . . . . . . . 86
(c) Freescale Semiconductor, Inc., 2010. All rights reserved.
Electrical Characteristics
support. In addition, the MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSEC), a DDR2 SDRAM memory controller, a SerDes block, an enhanced local bus controller (eLBC), an integrated programmable interrupt controller (IPIC), a general purpose DMA controller, two I2C controllers, dual UART (DUART), GPIOs, USB, general purpose timers, and an SPI controller. The high level of integration in the MPC8308 helps simplify board design and offers significant bandwidth and performance. A block diagram of the device is shown in Figure 1.
e300c3 Core with Power Management DUART I2C Timers GPIO, SPI 16-Kbyte I-Cache Interrupt Controller FPU 16-Kbyte D-Cache DMA Enhanced Local Bus DDR2 Controller
Enhanced Secure Digital Host Controller
PCI Express x1
USB 2.0 HS Host/Device/OTG ULPI
eTSEC1 RGMII,MII
eTSEC2 RGMII,MII
Figure 1. MPC8308 Block Diagram
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8308. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings1
Characteristic Symbol VDD AVDD1, AVDD2 GVDD Max Value -0.3 to 1.26 -0.3 to 1.26 -0.3 to 1.9 Unit V V V Notes -- -- --
Table 1 provides the absolute maximum ratings.
Core supply voltage PLL supply voltage DDR2 DRAM I/O voltage
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 2 Freescale Semiconductor
Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic Local bus, DUART, system control and power management, eSDHC, I2C, USB, Interrupt, Ethernet management, SPI, Miscellaneous and JTAG I/O voltage SERDES PHY Symbol NVDD Max Value -0.3 to 3.6 Unit V Notes 7
XCOREVDD, XPADVDD, SDAV DD LVDD1, LVDD2 MVIN MVREF LVIN OVIN
-0.3 to 1.26
V
--
eTSEC I/O Voltage Input voltage DDR2 DRAM signals DDR2 DRAM reference eTSEC Local bus, DUART, system control and power management, eSDHC, I2C, Interrupt, Ethernet management, SPI, Miscellaneous and JTAG I/O voltage Storage temperature range
-0.3 to 2.75 or -0.3 to 3.6 -0.3 to (GVDD + 0.3) -0.3 to (GVDD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (NVDD + 0.3)
V V V V V
6,8 2, 5 2, 5 4, 5,8 3, 5,7
TSTG
-55 to 150
C
--
Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed NVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: LV IN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M, L, O)VIN and MV REF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2 6. The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode. 7. NVDD here refers to NVDDA, NVDDB,NVDDG, NVDDH, NVDDP_K from the ball map. 8. LVDD1 here refers to NVDDC and LVDD2 refers to NVDDF from the ball map
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic SerDes internal digital power SerDes internal digital power SerDes I/O digital power SerDes analog power for PLL Symbol XCOREV DD XCOREVSS XPADVDD SDAVDD Recommended Value1 1.0 V 50 mV 0.0 1.0 V 50 mV 1.0 V 50 mV Unit V V V V
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 3
Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic SerDes analog power for PLL SerDes I/O digital power Core supply voltage Analog supply for e300 core APLL Analog supply for system APLL DDR2 DRAM I/O voltage Differential reference voltage for DDR controller Standard I/O voltage (Local bus, DUART, system control and power management, eSDHC, USB, I2C, Interrupt, Ethernet management, SPI, Miscellaneous and JTAG I/O voltage)2 eTSEC IO supply3,4 Analog and digital ground Junction temperature5 Notes:
1 2 3 4 5
Symbol SDAVSS XPADVSS VDD AVDD1 AVDD2 GV DD MVREF NVDD
Recommended Value1 0 0 1.0 V 50 mV 1.0 V 50 mV 1.0 V 50 mV 1.8 V 100 mV GVDD/2 (0.49 x GVDD to 0.51 x GVDD) 3.3 V 300 mV
Unit V V V V V V V V
LVDD1, LVDD2 VSS TA/TJ
2.5 V 125 mV 3.3 V 300 mV 0.0 0 to 105
V V C
GVDD, NVDD, AVDD, and VDD must track each other and must vary in the same direction--either in the positive or negative direction. NVDD here refers to NVDDA, NVDDB,NV DDG, NVDDH and NVDDP_K from the ball map. The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode. LVDD1 here refers to NVDDC and LVDD2 refers to NVDDF from the ball map. Minimum temperature is specified with TA; Maximum temperature is specified with TJ.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 4 Freescale Semiconductor
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device
G/L/NVDD + 20% G/L/NVDD + 5% VIH G/L/NVDD
VSS VSS - 0.3 V VIL VSS - 0.7 V Not to Exceed 10% of tinterface1
Note: 1. Note that tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
2.1.3
Output Driver Characteristics
Table 3. Output Driver Capability
Driver Type Output Impedance () 42 18 42 42 Supply Voltage NVDD = 3.3 V GVDD = 1.8 V NVDD = 3.3 V LVDD = 2.5/3.3 V
Table 3 provides information on the characteristics of the output driver strengths.
Local bus interface utilities signals DDR2 signals1
DUART, system control, I2C, JTAG, eSDHC, GPIO,SPI, USB eTSEC signals
1
Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR). For more information, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
2.1.4
Power Sequencing
The device does not require the core supply voltage (VDD) and I/O supply voltages (GVDD, LVDD, and NVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD, LVDD, and NVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 5
Power Characteristics
The I/O power supply ramp-up slew rate should be slower than 4V/100 s; this requirement is for ESD circuit. Note that there is no specific power-down sequence requirement for the device. I/O voltage supplies (GVDD, LVDD, and NVDD) do not have any ordering requirements with respect to one another.
V
I/O Voltage (GVDD, LVDD, and NVDD )
Core Voltage (VDD)
90%
0.7 V
0 PORESET >= 32 x tSYS_CLK_IN
t
Figure 3. Power-Up Sequencing Example
3
Power Characteristics
The estimated typical power dissipation, not including I/O supply power for the device is shown in Table 4. Table 5 shows the estimated typical I/O power dissipation.
Table 4. MPC8308 Power Dissipation1
Core Frequency (MHz) 266 333 400 Notes: The values do not include I/O supply power but do include core (AVDD) and PLL (AVDD1, AVDD2, XCOREV DD, XPADVDD, SDAVDD) 2 Typical power is based on best process, a voltage of VDD = 1.0V and ambient temperature of TA = 25 C 3 Maximum power is estimated based on best process, a voltage of VDD = 1.05 V and ambient temperature of TJ = 105 C
1
CSB Frequency (MHz) 133 133 133
Typical2 530 565 600
Maximum3 900 950 1000
Unit mW mW mW
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 6 Freescale Semiconductor
Clock Input Timing
Table 5 describes a typical scenario where blocks with the stated percentage of utilization and impedances consume the amount of power described.
1
Table 5. MPC8308 Typical I/O Power Dissipation
Interface DDR2 Rs = 22 Rt = 75 Local bus I/O load = 20 pF TSE C I/O load = 20 pF Parameter 250 MHz 32 bits+ECC 266 MHz 32 bits+ECC 62.5 MHz 66 MHZ MII, 25 MHz RGMII, 125 MHz eSDHC IO Load = 40 pF USB IO Load = 20 pF Other I/O 50 MHz 60 MHz -- GV DD (1.8 V) 0.302 0.309 -- -- -- -- -- -- 0.038 0.040 -- -- -- -- 0.017 -- 0.008 0.078 0.008 0.012 -- -- -- -- 0.044 -- W W W W W W -- -- -- -- 2 controllers NVDD (3.3 V) -- LVDD (3.3 V) -- LVDD (2.5 V) -- Unit W Comments --
4
4.1
Clock Input Timing
DC Electrical Characteristics
Table 6. SYS_CLK_IN DC Electrical Characteristics
Parameter Input high voltage Input low voltage SYS_CLK_IN input current Condition -- -- 0 V VIN NVDD Symbol VIH VIL IIN Min 2.4 -0.3 -- Max NVDD + 0.3 0.4 10 Unit V V A
This section provides the clock input DC and AC electrical characteristics for the device.
Table 6 provides the system clock input (SYS_CLK_IN) DC electrical specifications for the device.
Table 7 provides the RTC clock input (RTC_PIT_CLOCK) DC electrical specifications for the device.
Table 7. RTC_PIT_CLOCK DC Electrical Characteristics
Parameter Input high voltage Input low voltage Condition -- -- Symbol VIH VIL Min 3.3V - 400 mV 0 0.4 Max Unit V V
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 7
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the device is SYS_CLK_IN. Table 8 provides the system clock input (SYS_CLK_IN) AC timing specifications for the device.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter SYS_CLK_IN frequency SYS_CLK_IN period SYS_CLK_IN rise and fall time SYS_CLK_IN duty cycle SYS_CLK_IN Jitter Symbol fSYS_CLK_IN tSYS_CLK_IN tKH, tKL tKHK/tSYS_CLK_IN -- Min 24 15 0.6 40 -- -- -- Typ -- -- Max 66.67 41.67 1.2 60 150 Unit MHz ns ns % ps Notes 1, 6 -- 2 3 4, 5
Notes: 1. Caution: The system and core must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for SYS_CLK_IN are measured at 0.4 and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter--short term and long term--and is guaranteed by design. 5. The SYS_CLK_IN driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter. 6. Spread spectrum is allowed up to 1% down-spread @ 33 kHz (max rate).
Table 9. RTC_PIT_CLOCK AC Timing Specifications
Parameter RTC_PIT_CLOCK frequency RTC_PIT_CLOCK rise and fall time RTC_PIT_CLOCK duty cycle Symbol fRTC_PIT_CLOCK tRTCH, tRTCL tRTCHK/tRTC_PIT_CLO
CK
Min 1 1.5 45
Typ 32768 -- --
Max -- 3 55
Unit Hz s %
Notes -- -- --
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the device.
5.1
RESET DC Electrical Characteristics
Table 10. RESET Pins DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Symbol VIH VIL IIN VOH Condition -- -- 0 V VIN NVDD IOH = -8.0 mA 2.4 Min 2.0 -0.3 Max NVDD + 0.3 0.8 5 -- Unit V V A V
Table 10 provides the DC electrical characteristics for the RESET pins.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 8 Freescale Semiconductor
RESET Initialization
Table 10. RESET Pins DC Electrical Characteristics (continued)
Characteristic Output low voltage Output low voltage Symbol VOL VOL Condition IOL = 8.0 mA IOL = 3.2 mA Min -- -- Max 0.5 0.4 Unit V V
5.2
RESET AC Electrical Characteristics
Table 11. RESET Initialization Timing Specifications
Parameter/Condition Min 32 32 512 4 0 -- 1 Max -- -- -- -- -- 4 -- Unit tSYS_CLK_IN tSYS_CLK_IN tSYS_CLK_IN tSYS_CLK_IN ns ns ns Notes 1 -- 1 -- -- 2 1, 2
Table 11 provides the reset initialization AC timing specifications.
Required assertion time of HRESET (input) to activate reset flow Required assertion time of PORESET with stable power and clock applied to SYS_CLK_IN HRESET assertion (output) Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET Input hold time for POR configuration signals with respect to negation of HRESET Time for the device to turn off POR configuration signal drivers with respect to the assertion of HRESET Time for the device to turn on POR configuration signal drivers with respect to the negation of HRESET Notes: 1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN 2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]
Table 12 provides the PLL lock times.
Table 12. PLL Lock Times
Parameter/Condition System PLL lock time e300 core PLL lock time Min -- -- Max 100 100 Unit s s Notes -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 9
DDR2 SDRAM
6
DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR2 SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 1.7 0.49 x GVDD MVREF - 0.04 MVREF + 0.125 -0.3 -9.9 -13.4 13.4 Max 1.9 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MV REF - 0.125 9.9 -- -- Unit V V V V V A mA mA Notes 1 2 3 -- -- 4 -- --
Notes: 1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GV DD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 10 Freescale Semiconductor
DDR2 SDRAM
Table 15 provides the current draw characteristics for MVREF.
Table 15. Current Draw Characteristics for MVREF
Parameter/Condition Current draw for MV REF Symbol IMVREF Min -- Max 500 Unit A Note 1
Note: 1. The voltage regulator for MVREF must be able to supply up to 500 A current.
6.2
DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1
DDR2 SDRAM Input AC Timing Specifications
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface
Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8V.
At recommended operating conditions with GVDD of 1.8 100 mV
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.45
Max MVREF - 0.45 --
Unit V V
Notes -- --
Table 17 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 17. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 1.8 100 mV
Parameter Controller skew for MDQS--MDQ/MECC @266 MHz
Symbol tCISKEW
Min -875
Max 875
Unit ps
Notes 1, 2,3
Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called tDISKEW. This can be determined by the following equation: tDISKEW = +/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. Memory controller ODT value of 150 is recommended
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 11
DDR2 SDRAM
Figure 4 illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter.
MCK[n] MCK[n] tMCK
MDQS[n]
MDQ[x]/ MECC[x] tDISKEW
D0
D1 tDISKEW
Figure 4. Timing Diagram for tDISKEW
6.2.2
DDR2 SDRAM Output AC Timing Specifications
Table 18. DDR2 SDRAM Output AC Timing Specifications
Parameter Symbol 1 tMCK tDDKHAS 2.9 tDDKHAX 2.33 tDDKHCS -- ns 3 -- ns 3 Min 7.5 Max 10 Unit ns ns Notes 2 3
MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD output setup with respect to MCK 266 MHz ADDR/CMD output hold with respect to MCK 266 MHz MCS[n] output setup with respect to MCK
266 MHz MCS[n] output hold with respect to MCK 266 MHz MCK to MDQS Skew MDQ//MDM/MECC output setup with respect to MDQS 266 MHz MDQ//MDM/MECC output hold with respect to MDQS 266 MHz tDDKHDX, tDDKLDX tDDKHMH tDDKHDS, tDDKLDS tDDKHCX
3.15
-- ns 3
3.15 -0.6
-- 0.6 ns ps 4 5
900
-- ps 5
1100
--
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 12 Freescale Semiconductor
DDR2 SDRAM
Table 18. DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter MDQS preamble start MDQS epilogue end Symbol 1 tDDKHMP tDDKHME Min -0.5 x tMCK - 0.6 -0.6 Max -0.5 x tMCK + 0.6 0.6 Unit ns ns Notes 6 6
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. For a description and understanding of the timing modifications enabled by use of these bits, see the MPC8308 PowerQUICC II Pro Processor Reference Manual. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1.
Figure 5 shows the DDR2 SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns
MDQS tDDKHMH(min) = -0.6 ns
MDQS
Figure 5. Timing Diagram for tDDKHMH
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 13
DUART
Figure 6 shows the DDR2 SDRAM output timing diagram.
MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x]/ MECC[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 6. DDR2 SDRAM Output Timing Diagram
Figure 7 provides the AC test load for the DDR2 bus.
Output Z0 = 50 RL = 50 GVDD/2
Figure 7. DDR2 AC Test Load
7
7.1
DUART
DUART DC Electrical Characteristics
Table 19. DUART DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage NVDD High-level output voltage, IOH = -100 A Symbol VIH VIL VOH Min 2.1 -0.3 NVDD - 0.2 Max NVDD + 0.3 0.8 -- Unit V V V
This section describes the DC and AC electrical specifications for the DUART interface.
Table 19 provides the DC electrical characteristics for the DUART interface.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 14 Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 19. DUART DC Electrical Characteristics (continued)
Parameter Low-level output voltage, IOL = 100 A Input current (0 V VIN NVDD) Symbol VOL IIN Min -- -- Max 0.2 5 Unit V A
7.2
DUART AC Electrical Specifications
Table 20. DUART AC Timing Specifications
Parameter Minimum baud rate Maximum baud rate Oversample rate Value 256 > 1,000,000 16 Unit baud baud -- Notes -- 1 2
Table 20 provides the AC timing parameters for the DUART interface.
Notes: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample.
8
Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8308 supports dual Ethernet controllers.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)--MII/RGMII Electrical Characteristics
The electrical characteristics specified here apply to all the media independent interface (MII) and reduced gigabit media independent interface (RGMII) signals except management data input/output (MDIO) and management data clock (MDC). The RGMII interface is defined for 2.5 V, while the MII interface can be operated at 3.3 V. The RGMII interface follows the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3, "Ethernet Management Interface Electrical Characteristics."
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Ethernet: Three-Speed Ethernet, MII Management
8.1.1
eTSEC DC Electrical Characteristics
All MII and RGMII drivers and receivers comply with the DC parametric attributes specified in Table 21 and Table 22. The RGMII signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 21. MII DC Electrical Characteristics
Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL IOH = -4.0 mA IOL = 4.0 mA -- -- VIN 1 = LVDD VIN
1=
Conditions -- LVDD = Min LVDD= Min -- --
Min 3.0 2.40 VSS 2.1 -0.3 -- -600
Max 3.6 LVDD + 0.3 0.50 LVDD + 0.3 0.90 40 --
Unit V V V V V A A
VSS
Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 22. RGMII DC Electrical Characteristics
Parameters Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL IOH = -1.0 mA IOL = 1.0 mA -- -- Conditions -- LVDD = Min LVDD= Min LVDD = Min LVDD = Min VIN 1 = LVDD VIN 1 = VSS Min 2.37 2.00 VSS - 0.3 1.7 -0.3 -- -15 Max 2.63 LVDD + 0.3 0.40 LVDD + 0.3 0.70 15 -- Unit V V V V V A A
Note: 1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
8.2
MII and RGMII AC Timing Specifications
The AC timing specifications for MII and RGMII are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
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Ethernet: Three-Speed Ethernet, MII Management
8.2.1.1
MII Transmit AC Timing Specifications
Table 23. MII Transmit AC Timing Specifications
Table 23 provides the MII transmit AC timing specifications.
At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V 0.3V.
Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise VIL(min) to VIH(max) TX_CLK data clock fall VIH(max) to VIL(min)
Symbol 1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF
Min -- -- 35 1 1.0 1.0
Typ 400 40 -- 5 -- --
Max -- -- 65 15 4.0 4.0
Unit ns ns % ns ns ns
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 8 shows the MII transmit AC timing diagram.
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR
Figure 8. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
Table 24. MII Receive AC Timing Specifications
Table 24 provides the MII receive AC timing specifications.
At recommended operating conditions with LVDD /NVDD of 3.3 V 0.3V.
Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
Symbol 1 tMRX tMRX tMRXH/tMRX tMRDVKH
Min -- -- 35 10.0
Typ 400 40 -- --
Max -- -- 65 --
Unit ns ns % ns
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Ethernet: Three-Speed Ethernet, MII Management
Table 24. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD /NVDD of 3.3 V 0.3V.
Parameter/Condition RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min)
Symbol 1 tMRDXKH tMRXR tMRXF
Min 10.0 1.0 1.0
Typ -- -- --
Max -- 4.0 4.0
Unit ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 9 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR
Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications
Figure 10 provides the AC test load.
Output Z0 = 50 RL = 50 NVDD/2 or LVDD/2
Figure 10. AC Test Load
8.2.2
RGMII AC Timing Specifications
Table 25. RGMII AC Timing Specifications
Table 25 presents the RGMII AC timing specifications.
At recommended operating conditions with LVDD of 2.5 V 5%.
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver)
2
Symbol 1 tSKRGT tSKRGT
Min -0.6 1.0
Typ -- --
Max 0.6 2.6
Unit ns ns
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Ethernet: Three-Speed Ethernet, MII Management
Table 25. RGMII AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 2.5 V 5%.
Clock cycle duration 3 Duty cycle for 1000Base-T
4, 5 3, 5
tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG12
6
7.2 45 40 -- -- -- 47
8.0 50 50 -- -- 8.0 --
8.8 55 60 0.75 0.75 -- 53
ns % % ns ns ns %
Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle
tG125H/tG125
Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing. For example, the subscript of tRGT represents the RGMII receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Duty cycle reference is 0.5*LVDD 6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
Figure 11 shows the RGMII AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY)
TX_CTL
RXD[8:5][3:0] RXD[7:4][3:0]
RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT
RX_CTL
RX_CLK (At PHY)
Figure 11. RGMII AC Timing and Multiplexing Diagrams
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Ethernet: Three-Speed Ethernet, MII Management
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for MII and RGMII are specified in Section 8.1, "Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)--MII/RGMII Electrical Characteristics."
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. Table 26 provides the DC electrical characteristics for MDIO and MDC.
Table 26. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol NVDD VOH VOL VIH VIL IIH IIL NVDD = Max NVDD = Max IOH = -1.0 mA IOL = 1.0 mA -- -- VIN
1
Conditions -- NVDD = Min LVDD = Min
Min 3.0 2.10 VSS 2.0 -- = 2.1 V -- -600
Max 3.6 NVDD + 0.3 0.50 -- 0.80 40 --
Unit V V V V V A A
VIN = 0.5 V
Note: 1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
8.3.2
MII Management AC Electrical Specifications
Table 27. MII Management AC Timing Specifications
Table 27 provides the MII management AC timing specifications.
At recommended operating conditions with LVDDA/LVDDB is 3.3 V 0.3V
Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time
Symbol 1 fMDC tMDC tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR
Min -- -- 32 10 5 0 --
Typ 2.5 400 -- -- -- -- --
Max -- -- -- 170 -- -- 10
Unit MHz ns ns ns ns ns ns
Notes 2 -- -- 3 -- -- --
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Ethernet: Three-Speed Ethernet, MII Management
Table 27. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB is 3.3 V 0.3V
Parameter/Condition MDC fall time
Symbol 1 tMDHF
Min --
Typ --
Max 10
Unit ns
Notes --
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency of the Mgmt Clock EC_MDC.) 3. This parameter is dependent on the cbs_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns).
Figure 12 shows the MII management AC timing diagram.
tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR
Figure 12. MII Management Interface Timing Diagram
8.4
IEEE Std 1588TM Timer Specifications
This section describes the DC and AC electrical specifications for the 1588 timer.
8.4.1
IEEE 1588 Timer DC Specifications
Table 28. GPIO DC Electrical Characteristics
Characteristic Symbol VOH VOL VOL VIH Condition IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA -- Min 2.4 -- -- 2.0 Max -- 0.5 0.4 NVDD + 0.3 Unit V V V V
Table 28 provides the IEEE 1588 timer DC specifications.
Output high voltage Output low voltage Output low voltage Input high voltage
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USB
Table 28. GPIO DC Electrical Characteristics (continued)
Characteristic Input low voltage Input current Symbol VIL IIN Condition -- 0 V VIN NVDD Min -0.3 -- Max 0.8 5 Unit V A
8.4.2
IEEE 1588 Timer AC Specifications
Table 29. IEEE 1588 Timer AC Specifications
Parameter Symbol tTMRCK tTMRCKS tTMRCKH tGCLKNV tTMRAL Min 0 -- -- 0 -- Max 70 -- -- 6 -- Unit MHz -- -- ns -- Notes 1 2, 3 2, 3 -- 2
Table 29 provides the IEEE 1588 timer AC specifications.
Timer clock cycle time Input setup to timer clock Input hold from timer clock Output clock to output valid Timer alarm to output valid
Notes: 1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. 2. Asynchronous signals. 3. Inputs need to be stable at least one TMR clock.
9
9.1
USB
USB Dual-Role Controllers
This section provides the AC and DC electrical specifications for the USB-ULPI interface.
9.1.1
USB DC Electrical Characteristics
Table 30. USB DC Electrical Characteristics
Parameter Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- LVDD - 0.2 -- Max LVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V
Table 30 lists the DC electrical characteristics for the USB interface.
High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A
Note: 1. The symbol VIN, in this case, represents the NV IN symbol referenced in Table 1 and Table 2.
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USB
9.1.2
USB AC Electrical Specifications
Table 31. USB General Timing Parameters
Parameter Symbol 1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOX Min 15 4 1 -- 1 Max -- -- -- 9 -- Unit ns ns ns ns ns Notes 1, 2 1, 4 1, 4 1 1
Table 31 lists the general timing parameters of the USB-ULPI interface.
USB clock cycle time Input setup to USB clock--all inputs Input hold to USB clock--all inputs USB clock to output valid--all outputs Output hold from USB clock--all outputs
Notes: 1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state)(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t USKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from NVDD/2 of the rising edge of USB clock to 0.4 x NVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
Figure 13 and Figure 14 provide the AC test load and signals for the USB, respectively.
Output Z0 = 50 RL = 50 NVDD/2
Figure 13. USB AC Test Load
USBDR_CLK tUSIVKH Input Signals tUSIXKH
tUSKHOV Output Signals
tUSKHOX
Figure 14. USB Signals
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High-Speed Serial Interfaces (HSSI)
10 High-Speed Serial Interfaces (HSSI)
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane's transmitter and receiver reference circuits are also shown.
10.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 15 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (TXn and TXn) or a receiver input (RXn and RXn). Each signal swings between A Volts and B Volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input signals TXn, TXn, RXn, and RXn each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire's single-ended swing. 2. Differential Output Voltage, VOD (or Differential Output Swing) The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VTXn - VTXn. The VOD value can be either positive or negative. 3. Differential Input Voltage, VID (or Differential Input Swing) The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VRXn - VRXn. The VID value can be either positive or negative. 4. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, VDIFFp = |A - B| Volts. 5. Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2*|VOD|. 6. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (TXn, for example) from the non-inverting signal (TXn, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 24 as an example for differential waveform.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 24 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
7. Common Mode Voltage, Vcm The common mode voltage is equal to one-half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VTXn + VTXn )/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It is also referred as the DC offset in some occasion.
TXn or RXn A Volts
Vcm = (A + B) / 2 TXn or RXn B Volts
Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Figure 15. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (current mode logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV; in other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
10.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK for PCI Express. The following sections describe the SerDes reference clock requirements and some application information.
10.2.1
SerDes Reference Clock Receiver Characteristics
Figure 16 shows a receiver reference diagram of the SerDes reference clocks.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 25
High-Speed Serial Interfaces (HSSI)
* *
*
*
The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2. SerDes reference clock receiver reference circuit structure -- The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 16. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50- termination to XCOREVSS followed by on-chip AC-coupling. -- The external reference clock driver must be able to drive this termination. -- The SerDes reference clock input can be either differential or single ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements. The maximum average current requirement that also determines the common mode voltage range -- When the SerDes reference clock differential inputs are DC-coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. -- This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above XCOREVSS. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV. -- If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 to XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. The input amplitude requirement -- This requirement is described in detail in the following sections.
50 SD_REF_CLK Input Amp SD_REF_CLK 50
Figure 16. Receiver of SerDes Reference Clocks
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 26 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
10.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. * Differential Mode -- The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. -- For external DC-coupled connection, as described in Section 10.2.1, "SerDes Reference Clock Receiver Characteristics," the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 17 shows the SerDes reference clock input requirement for DC-coupled connection scheme. -- For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (XCOREVSS). Figure 18 shows the SerDes reference clock input requirement for AC-coupled connection scheme. * Single-Ended Mode -- The reference clock can also be single ended. The SD_REF_CLK input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax) with SD_REF_CLK either left unconnected or tied to ground. -- The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 19 shows the SerDes reference clock input requirement for single-ended signaling mode. -- To meet the input amplitude requirement, the reference clock inputs might need to be DC- or AC-coupled externally. For the best noise performance, the reference of the clock could be DCor AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 27
High-Speed Serial Interfaces (HSSI)
SD_REF_CLK
200 mV < Input Amplitude or Differential Peak < 800 mV Vmax < 80 0mV
100 mV < Vcm < 400 mV
SD_REF_CLK
Vmin > 0 V
Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled)
200mV < Input Amplitude or Differential Peak < 800mV SD_REF_CLK Vmax < Vcm + 400 mV
Vcm
SD_REF_CLK
Vmin > Vcm - 400 mV
Figure 18. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SD_REF_CLK Input Amplitude < 800 mV
SD_REF_CLK
0V SD_REF_CLK
Figure 19. Single-Ended Reference Clock Input DC Requirements
10.2.3
Interfacing with Other Differential Signaling Levels
With on-chip termination to XCOREVSS, the differential reference clocks inputs are high-speed current steering logic (HCSL)-compatible and DC-coupled. Many other low-voltage differential type outputs like low-voltage differential signaling (LVDS) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100-400 mV) for DC-coupled connection. LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling.
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High-Speed Serial Interfaces (HSSI)
NOTE Figure 20 to Figure 23 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance, and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8308 SerDes reference clock receiver requirement provided in this document. Figure 20 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8308 SerDes reference clock input's DC requirement.
HCSL CLK Driver Chip
CLK_Out 33 SD_REF_CLK 50
MPC8308
Clock Driver 33 CLK_Out
100 differential PWB trace
SerDes Refer. CLK Receiver
SD_REF_CLK
50
Total 50 . Assume clock driver's output impedance is about 16 .
Clock driver vendor dependent source termination resistor
Figure 20. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
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High-Speed Serial Interfaces (HSSI)
Figure 21 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver's common mode voltage is higher than the MPC8308's SerDes reference clock input's allowed range (100-400 mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50- termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component.
LVDS CLK Driver Chip
CLK_Out 10 nF SD_REF_CLK 50
MPC8308
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
CLK_Out
10 nF
SD_REF_CLK
50
Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 30 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 22 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver's DC levels (both common mode voltages and output swing) are incompatible with MPC8308 SerDes reference clock input's DC requirement, AC-coupling has to be used. Figure 22 assumes that the LVPECL clock driver's output impedance is 50 . R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 depending on clock driver vendor's requirement. R2 is used together with the SerDes reference clock receiver's 50- termination resistor to attenuate the LVPECL output's differential peak level such that it meets the MPC8308's SerDes reference clock's differential input amplitude requirement (between 200 mV and 800 mV differential peak). For example, if the LVPECL output's differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 . Consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.
LVPECL CLK Driver Chip
CLK_Out R2 10nF SD_REF_CLK
MPC8308
50
Clock Driver
R1
100 differential PWB trace R2 10 nF SD_REF_CLK
SerDes Refer. CLK Receiver
CLK_Out R1
50
Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 31
High-Speed Serial Interfaces (HSSI)
Figure 23 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with the device's SerDes reference clock input's DC requirement.
Single-Ended CLK Driver Chip
Total 50 . Assume clock driver's output impedance is about 16 . 33 CLK_Out SD_REF_CLK 50
MPC8308
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
50
SD_REF_CLK
50
Figure 23. Single-Ended Connection (Reference Only)
10.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high-quality reference clock with low-phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops, and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15 MHz range. The source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. Table 32 describes some AC parameters for PCI Express protocol.
Table 32. SerDes Reference Clock AC Parameters
At recommended operating conditions with XCOREVDD= 1.0V 5%
Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage
Symbol Rise Edge Rate Fall Edge Rate VIH VIL
Min 1.0 1.0 +200 --
Max 4.0 4.0 -- -200
Unit V/ns V/ns mV mV
Notes 2, 3 2, 3 2 2
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 32 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Table 32. SerDes Reference Clock AC Parameters (continued)
At recommended operating conditions with XCOREVDD= 1.0V 5%
Parameter Rising edge rate (SD_REF_CLK) to falling edge rate (SD_REF_CLK) matching
Symbol Rise-Fall Matching
Min --
Max 20
Unit %
Notes 1, 4
Notes: 1. Measurement taken from single-ended waveform. 2. Measurement taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing (Figure 24). 4. Matching applies to rising edge rate for SD_REF_CLK and falling edge rate for SD_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SD_REF_CLK should be compared to the Fall Edge Rate of SD_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate (See Figure 25).
VIH
=
+200 0.0 V
VIL = -200 mV SD_REF_CLK minus SD_REF_CLK
Figure 24. Differential Measurement Points for Rise and Fall Time
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
Figure 25. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application usage. For detailed information, see Section 11.2, "AC Requirements for PCI Express SerDes Clocks."
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 33
PCI Express
10.2.4.1
Spread Spectrum Clock
SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source.
10.3
SerDes Transmitter and Receiver Reference Circuits
Figure 26 shows the reference circuits for SerDes data lane's transmitter and receiver.
TXn 50 Transmitter 50 TXn RXn 50 50 Receiver RXn
Figure 26. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in Section 11, "PCI Express." Note that external AC-coupling capacitor is required for the PCI Express serial transmission protocol with the capacitor value defined in specification of PCI Express protocol section.
11 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus.
11.1
DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK
For more information, see Section 10.2, "SerDes Reference Clocks."
11.2
AC Requirements for PCI Express SerDes Clocks
Table 33. SD_REF_CLK and SD_REF_CLK AC Requirements
Table 33 lists the PCI Express SerDes clock AC requirements.
Symbol tREF tREFCJ tREFPJ
Parameter Description REFCLK cycle time (for 125 MHz and 100 MHz) REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles. Phase jitter. Deviation in edge location with respect to mean edge location.
Min 8 -- -50
Typ 10 -- --
Max -- 100 50
Units ns ps ps
Notes -- -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 34 Freescale Semiconductor
PCI Express
11.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a 300 ppm tolerance.
11.4
Physical Layer Specifications
Following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer, use the PCI Express Base Specification, Rev. 1.0a.
11.4.1
Differential Transmitter (TX) Output
Table 34 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins.
Table 34. Differential Transmitter (TX) Output Specifications
Parameter Unit interval Symbol UI Comments Each UPETX is 400 ps 300 ppm. U PETX does not account for Spread Spectrum Clock dictated variations. VPEDPPTX = 2*|VTX-D+ VTX-D-| Ratio of the VPEDPPTX of the second and following bits after a transition divided by the VPEDPPTX of the first bit after a transition. The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 UPEEWTX= 0.3 UI. Min 399.88 Typical 400 Max 400.12 Units ps Notes 1
Differential peak-to-peak output voltage De-emphasized differential output voltage (ratio)
VTX-DIFFp-p VTX-DE-RATIO
0.8 -3.0
-- -3.5
1.2 -4.0
V dB
2 2
Minimum TX eye width
TTX-EYE
0.70
--
--
UI
2, 3
Maximum time between the jitter median and maximum deviation from the median
TTX-EYE-MEDIAN-t Jitter is defined as the measurement variation of othe crossing points MAX-JITTER (VPEDPPTX = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
--
--
0.15
UI
2, 3
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 35
PCI Express
Table 34. Differential Transmitter (TX) Output Specifications (continued)
Parameter D+/D- TX output rise/fall time RMS AC peak common mode output voltage Symbol TTX-RISE, TTX-FALL VTX-CM-ACp Comments -- VPEACPCMTX = RMS(|VTXD+ + VTXD-|/2 VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 |VTX-CM-DC (during L0) VTX-CM-Idle-DC (During Electrical Idle)|<=100 mV VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 [L0] VTX-CM-Idle-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 [Electrical Idle] Min 0.125 -- Typical -- -- Max -- 20 Units UI mV Notes 2, 5 2
Absolute delta of DC common mode voltage during L0 and electrical idle
VTX-CM-DCACTIVEIDLE-DELTA
0
--
100
mV
2
Absolute delta of DC common mode between D+ and D-
VTX-CM-DC-LINE- |VTX-CM-DC-D+ VTX-CM-DC-D-| <= 25 mV DELTA VTX-CM-DC-D+ = DC (avg) of |VTX-D+| VTX-CM-DC-D- = DC (avg) of |VTX-D-| VTX-IDLE-DIFFp VPEEIDPTX = |VTX-IDLE-D+ -VTX-IDLE-D-| <= 20 mV
0
--
25
mV
2
Electrical idle differential peak output voltage
0 --
-- 600
20 --
mV mV
2 6
Amount of voltage change VTX-RCV-DETECT The total amount of allowed during receiver voltage change that a detection transmitter can apply to sense whether a low impedance Receiver is present. TX DC common mode voltage TX short circuit current limit Minimum time spent in electrical idle VTX-DC-CM The allowed DC Common Mode voltage under any conditions. The total current the Transmitter can provide when shorted to its ground Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set
--
3.6
--
V
6
ITX-SHORT
--
--
90
mA
--
TTX-IDLE-MIN
50
--
--
UI
--
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 36 Freescale Semiconductor
PCI Express
Table 34. Differential Transmitter (TX) Output Specifications (continued)
Parameter Maximum time to transition to a valid electrical idle after sending an electrical idle ordered set Symbol Comments Min -- Typical -- Max 20 Units UI Notes --
TTX-IDLE-SET-TO-I After sending an Electrical Idle ordered set, the DLE Transmitter must meet all Electrical Idle Specifications within this time. This is considered a debounce time for the Transmitter to meet Electrical Idle after transitioning from L0. Maximum time to meet all TX specifications when transitioning from Electrical Idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving Electrical Idle Measured over 50 MHz to 1.25 GHz. Measured over 50 MHz to 1.25 GHz. TX DC Differential mode Low Impedance Required TX D+ as well as D- DC Impedance during all states Static skew between any two Transmitter Lanes within a single Link All Transmitters are AC-coupled. The AC-coupling is required either within the media or within the transmitting component itself. An external capacitor of 100nF is recommended.
TTX-IDLE-TO-DIFFMaximum time to transition to valid TX DATA specifications after leaving an electrical idle condition
--
--
20
UI
--
Differential return loss Common mode return loss DC differential TX impedance Transmitter DC impedance Lane-to-Lane output skew
RLTX-DIFF RLTX-CM ZTX-DIFF-DC ZTX-DC
12 6 80 40
-- -- 100 --
-- -- 120 --
dB dB
4 4 -- --
LTX-SKEW
--
--
500 + 2 UI 200
ps
--
AC-coupling capacitor
CTX
75
--
nF
--
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 37
PCI Express
Table 34. Differential Transmitter (TX) Output Specifications (continued)
Parameter Crosslink random timeout Symbol Tcrosslink Comments This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one Downstream and one Upstream Port. Min 0 Typical -- Max 1 Units ms Notes 7
Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 29 and measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 27.) 3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The transmitter input impedance results in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes, see Figure 29). Note that the series capacitors, CTX, is optional for the return loss measurement. 5. Measured between 20% and 80% at transmitter package pins into a test load as shown in Figure 29 for both VTX-D+ and VTX-D-. 6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a. 7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
11.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 27 is specified using the passive compliance/test measurement load (Figure 29) in place of any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. NOTE It is recommended that the recovered TX UI be calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits).
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 38 Freescale Semiconductor
PCI Express
V TX-DIFF = 0 mV (D+ D- Crossing Point) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV
V TX-DIFF = 0 mV (D+ D- Crossing Point)
[De-emphasized Bit] 566 mV (3 dB) >= V TX-DIFFp-p-MIN >= 505 mV (4 dB)
0.7 UI = UI - 0.3 UI(JTX-TOTAL-MAX) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV
Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications
11.4.3
Differential Receiver (RX) Input Specifications
Table 35 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins.
Table 35. Differential Receiver (RX) Input Specifications
Parameter Unit interval Symbol UI Comments Each UPERX is 400 ps 300 ppm. UPERX does not account for Spread Spectrum Clock dictated variations. VPEDPPRX = 2*|VRX-D+ VRX-D-| The maximum interconnect media and Transmitter jitter that can be tolerated by the Receiver can be derived as TRX-MAX-JITTER = 1 UPEEWRX= 0.6 UI. Min 399.88 Typical 400 Max 400.12 Units ps Notes 1
Differential peak-to-peak output voltage Minimum receiver eye width
VRX-DIFFp-p TRX-EYE
0.175 0.4
-- --
1.200 --
V UI
2 2, 3
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 39
PCI Express
Table 35. Differential Receiver (RX) Input Specifications (continued)
Parameter Maximum time between the jitter median and maximum deviation from the median. Symbol Comments Min -- Typical -- Max 0.3 Units UI Notes 2, 3, 7
TRX-EYE-MEDIAN-t Jitter is defined as the measurement variation of o-MAX-JITTER the crossing points (VPEDPPRX = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. VRX-CM-ACp VPEACPCMRX = |VRXD+ + VRXD-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2 Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 mV and -300 mV, respectively. Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at 0 V. RX DC differential mode impedance. Required RX D+ as well as D- DC Impedance (50 20% tolerance).
AC peak common mode input voltage
--
--
150
mV
2
Differential return loss
RLRX-DIFF
15
--
--
dB
4
Common mode return loss DC differential input impedance DC Input Impedance
RLRX-CM
6
--
--
dB
4
ZRX-DIFF-DC ZRX-DC
80 40
100 50
120 60

5 2, 5
Powered down DC input impedance
ZRX-HIGH-IMP-DC Required RX D+ as well as D- DC Impedance when the Receiver terminations do not have power. VRX-IDLE-DET-DIF VPEEIDT = 2*|VRX-D+ -VRX-D-| Fp-p Measured at the package pins of the Receiver
200 k
--
--
6
Electrical idle detect threshold
65
--
175
mV --
Unexpected Electrical Idle TRX-IDLE-DET-DIFF An unexpected Electrical Enter Detect Threshold Idle (Vrx-diffp-p < Integration Time Vrx-idle-det-diffp-p) must ENTERTIME be recognized no longer than Trx-idle-det-diff-entertime to signal an unexpected idle condition.
--
--
10
ms --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 40 Freescale Semiconductor
PCI Express
Table 35. Differential Receiver (RX) Input Specifications (continued)
Parameter Total Skew Symbol LRX-SKEW Comments Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (for example, COM and one to five SKP Symbols) at the RX as well as any delay differences arising from the interconnect itself. Min -- Typical -- Max 20 Units ns -- Notes
Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 29 should be used as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 28). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4. The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 to ground for both the D+ and D- line (that is, as measured by a vector network analyzer with 50- probes, see Figure 29). Note that the series capacitors, CTX, is optional for the return loss measurement. 5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground. 7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
11.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 28 is specified using the passive compliance/test measurement load (Figure 29) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram measured with the compliance/test measurement load (Figure 29) is larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics that cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 28) expected at the input receiver based on an adequate combination of system simulations and the return loss measured looking into the RX package
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 41
PCI Express
and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 probes--see Figure 29). Note that the series capacitors, CPEACCTX, are optional for the return loss measurement.
VRX-DIFF = 0 mV (D+ D- Crossing Point) VRX-DIFF = 0 mV (D+ D- Crossing Point)
V RX-DIFFp-p-MIN > 175 mV
0.4 UI = T RX-EYE-MIN
Figure 28. Minimum Receiver Eye Timing and Voltage Compliance Specification
11.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 29. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 42 Freescale Semiconductor
Enhanced Local Bus
Figure 29. Compliance Test/Measurement Load
12 Enhanced Local Bus
This section describes the DC and AC electrical specifications for the enhanced local bus interface.
12.1
Enhanced Local Bus DC Electrical Characteristics
Table 36. Local Bus DC Electrical Characteristics at 3.3 V
Parameter Symbol VIH VIL IIN VOH VOL Min 2.0 -0.3 -- NVDD - 0.2 -- Max NVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V
Table 36 provides the DC electrical characteristics for the local bus interface.
High-level input voltage Low-level input voltage Input current, (VIN1 = 0 V or VIN = LVDD) High-level output voltage, (LVDD = min, IOH = -2 mA) Low-level output voltage, (LVDD = min, IOH = 2 mA)
Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned.
12.2
Enhanced Local Bus AC Electrical Specifications
Table 37. Local Bus General Timing Parameters
Parameter Symbol 1 tLBK tLBIVKH tLBIXKH Min 15 7 1 Max -- -- -- Unit ns ns ns Notes 2 3, 4 3, 4
Table 37 describes the general timing parameters of the local bus interface.
Local bus cycle time Input setup to local bus clock (Note: to be revisited) Input hold from local bus clock (Note: to be revisited)
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 43
Enhanced Local Bus
Table 37. Local Bus General Timing Parameters (continued)
Parameter Local bus clock to output valid (Note: to be revisited) Local bus clock to output high impedance for LD (Note: to be revisited) Symbol 1 tLBKHOV tLBKHOZ Min -- -- Max 3 4 Unit ns ns Notes 3 5
Notes: 1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). 2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 x NVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
Figure 30 provides the AC test load for the local bus.
Output Z0 = 50 RL = 50 NVDD/2
Figure 30. Local Bus AC Test Load
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 44 Freescale Semiconductor
Enhanced Local Bus
Figure 31 through Figure 33 show the local bus signals. In what follows, T1, T2, T3, and T4 are internal clock reference phase signals corresponding to LCCR[CLKDIV].
LCLK0 tLBIVKH Input Signals: LD[0:15] tLBIVKH Input Signal: LGTA tLBIXKH Output Signals: tLBKHOV tLBIXKH tLBIXKH
LBCTL//LOE/ Output Signals: LA[0:25]
tLBKHOV
tLBKHOZ
Figure 31. Local Bus Signals, Non-Special Signals Only
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 45
Enhanced Local Bus
LCLK0
T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ
Input Signals: LD[0:15] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ
Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 46 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
LCLK
T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ
Input Signals: LD[0:15] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ
Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4
13 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC/SDIO) interface of the MPC8308. The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the SD_DAT[0:3]/CMD as outputs and rising edge to sample the SD_DAT[0:3], CMD, CD, and WP as inputs. This behavior is true for both full- and high-speed modes.
13.1
eSDHC DC Electrical Characteristics
Table 38 provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device, compatible with SDHC specifications. The eSDHC NVDD range is between 3.0 V and 3.6 V.
Table 38. eSDHC interface DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Symbol VOH VOL Condition IOH = -8.0 mA IOL = 8.0 mA Min 2.4 -- Max -- 0.5 Unit V V
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 47
Enhanced Secure Digital Host Controller (eSDHC)
Table 38. eSDHC interface DC Electrical Characteristics (continued)
Characteristic Output low voltage Input high voltage Input low voltage Symbol VOL VIH VIL Condition IOL = 3.2 mA -- -- Min -- 2.1 -0.3 Max 0.4 NVDD + 0.3 0.8 Unit V V V
13.2
eSDHC AC Timing Specifications (Full-Speed Mode)
This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device. Table 39 provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 35 and Figure 36.
Table 39. eSDHC AC Timing Specifications for Full-Speed Mode
At recommended operating conditions NV DD = 3.3 V 300 mV.
Parameter SD_CLK clock frequency--full-speed mode SD_CLK clock cycle SD_CLK clock frequency--identification mode SD_CLK clock low time SD_CLK clock high time SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx to SD_CLK Input hold times: SD_CMD, SD_DATx to SD_CLK Output valid: SD_CLK to SD_CMD, SD_DATx valid Output hold: SD_CLK to SD_CMD, SD_DATx valid SD card input setup SD card input hold SD card output valid SD card output hold
Symbol 1 fSFSCK tSFSCK fSIDCK tSFSCKL tSFSCKH tSFSCKR/ tSFSCKF tSFSIVKH tSFSIXKH tSFSKHOV tSFSKHOX tISU tIH tODLY tOH
Min 0 40 0 15 15 -- 3 2 -- -3 5 5 -- 0
Max 25 -- 400 -- -- 5 -- -- 3 -- -- -- 14 --
Unit MHz ns kHz ns ns ns ns ns ns -- ns ns ns ns
Notes -- -- -- 2 2 2 2 2 2 -- 3 3 3 3
Notes: 1 The symbols used for timing specifications herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also tSFSKHOV symbolizes eSDHC full-speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 48 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
Figure 34 provides the eSDHC clock input timing diagram.
eSDHC External Clock operational mode VM VM VM tSFSCKL tSFSCK VM = Midpoint Voltage (NVDD/2) tSFSCKR tSFSCKF tSFSCKH
Figure 34. eSDHC Clock Input Timing Diagram
13.2.1
Full-Speed Output Path (Write)
Figure 35 provides the data and command output timing diagram.
tSFSCK (Clock Cycle) SD CLK at the MPC8308 Pin Driving Edge tCLK_DELAY SD CLK at the Card Pin Output Valid Time: tSFSKHOV Output Hold Time: tSFSKHOX Output from the MPC8308 Pins tSFSCKL Sampling Edge
Input at the MPC8308 Pins tDATA_DELAY tISU (5 ns) tIH (5 ns)
Figure 35. Full-Speed Output Path
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 49
Enhanced Secure Digital Host Controller (eSDHC)
13.2.2
Full-Speed Input Path (Read)
Figure 36 provides the data and command input timing diagram.
tSFSCK (Clock Cycle) SD CLK at the MPC8308 Pin tCLK_DELAY SD CLK at the Card Pin Driving Edge tODLY tOH Output from the SD Card Pins Sampling Edge
tDATA_DELAY
Input at the MPC8308 Pins tSFSIXKH tSFSIVKH (MPC8308 Input Hold)
Figure 36. Full-Speed Input Path
13.3
eSDHC AC Timing Specifications
Table 40. eSDHC AC Timing Specifications for High-Speed Mode
Table 40 provides the eSDHC AC timing specifications.
At recommended operating conditions NVDD = 3.3 V 300 mV.
Parameter SD_CLK clock frequency--high-speed mode SD_CLK clock cycle SD_CLK clock frequency--identification mode SD_CLK clock low time SD_CLK clock high time SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx Input hold times: SD_CMD, SD_DATx Output delay time: SD_CLK to SD_CMD, SD_DATx valid Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid SD Card Input Setup SD Card Input Hold
Symbol 1 fSHSCK tSHSCK fSIDCK tSHSCKL tSHSCKH tSHSCKR/ tSHSCKF tSHSIVKH tSHSIXKH tSHSKHOV tSHSKHOX tISU tIH
Min 0 20 0 7 7 -- 3 2 3 -3 6 2
Max 50 -- 400 -- -- 3 -- -- -- -- -- --
Unit MHz ns kHz ns ns ns ns ns ns ns ns ns
Notes 3 -- -- 2 2 2 2 2 2 2 3 3
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 50 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
Table 40. eSDHC AC Timing Specifications for High-Speed Mode (continued)
At recommended operating conditions NVDD = 3.3 V 300 mV.
Parameter SD Card Output Valid SD Card Output Hold
1
Symbol 1 tODLY tOH
Min -- 2.5
Max 14 --
Unit ns ns
Notes 3 3
Notes: The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also tSFSKHOV symbolizes eSDHC full-speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications.
Figure 37 provides the eSDHC clock input timing diagram.
eSDHC External Clock operational mode VM VM VM tSHSCKL tSHSCK VM = Midpoint Voltage (NVDD/2) tSHSCKR tSHSCKF tSHSCKH
Figure 37. eSDHC Clock Input Timing Diagram
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 51
Enhanced Secure Digital Host Controller (eSDHC)
13.3.1
High-Speed Output Path (Write)
Figure 38 provides the data and command output timing diagram.
tSHSCK (Clock Cycle) SD CLK at the MPC8308 Pin Driving Edge tCLK_DELAY SD CLK at the Card Pin Output Valid Time: tSHSKHOV Output Hold Time: tSHSKHOX Output from the MPC8308 Pins tSHSCKL Sampling Edge
Input at the SD Card Pins tDATA_DELAY tISU (6 ns) tIH (2 ns)
Figure 38. High-Speed Output Path
13.3.2
High-Speed Input Path (Read)
Figure 39 provides the data and command input timing diagram.
tSHSCK (Clock Cycle) 1/2 Cycle SD CLK at the MPC8308 Pin tCLK_DELAY SD CLK at the Card Pin Driving Edge tODLY tOH Output from the SD Card Pins tDATA_DELAY Sampling Edge
Input at the MPC8308 Pins tSHSIVKH (MPC8308 Input (MPC8308 Input tSHSIXKH
Figure 39. High-Speed Input Path
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 52 Freescale Semiconductor
JTAG
14 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std 1149.1TM (JTAG) interface.
14.1
JTAG DC Electrical Characteristics
Table 41. JTAG Interface DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL Condition -- -- -- IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Min 2.1 -0.3 Max NVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
Table 41 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface.
14.2
JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface. Table 42 provides the JTAG AC timing specifications as defined in Figure 41 through Figure 44.
Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1
At recommended operating conditions (see Table 2).
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO
Symbol2 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV
Min 0 30 15 0 25 4 4 10 10 2 2
Max 33.3 -- -- 2 -- -- --
Unit MHz ns ns ns ns ns
Notes -- -- -- -- 3 4
ns -- -- ns 11 11 5 4
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 53
JTAG
Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1 (continued)
At recommended operating conditions (see Table 2).
Parameter Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO
Symbol2
Min
Max
Unit
Notes
tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ
2 2 2 2
-- -- 19 9
ns
5
ns
5, 6
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 40). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization.
Figure 40 provides the AC test load for TDO and the boundary-scan outputs.
Output Z0 = 50 R L = 50 NVDD/2
Figure 40. AC Test Load for the JTAG Interface
Figure 41 provides the JTAG clock input timing diagram.
JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (NV DD/2) VM VM tJTGR tJTGF
Figure 41. JTAG Clock Input Timing Diagram
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 54 Freescale Semiconductor
JTAG
Figure 42 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (NVDD/2) VM
Figure 42. TRST Timing Diagram
Figure 43 provides the boundary-scan timing diagram.
JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (NVDD /2) Output Data Valid Input Data Valid VM
Figure 43. Boundary-Scan Timing Diagram
Figure 44 provides the test access port timing diagram.
JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (NVDD/2) Output Data Valid Input Data Valid VM
Figure 44. Test Access Port Timing Diagram
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 55
I2C
15 I2C
This section describes the DC and AC electrical characteristics for the I2C interface.
15.1
I2C DC Electrical Characteristics
Table 43. I2C DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the I2C interface.
At recommended operating conditions with NVDD of 3.3 V 0.3 V.
Parameter Input high-voltage level Input low-voltage level Low-level output voltage High-level output voltage Output fall time from VIH(min) to V IL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Input current, (0 V VIN NVDD)
Symbol VIH VIL VOL VOH
Min 0.7 x NV DD -0.3 0 0.8 x NVDD
Max NVDD + 0.3 0.3 x NVDD 0.2 x NVDD NVDD + 0.3 250 50 10 5
Unit Notes V V V V ns ns pF A -- -- 1 -- 2 3 -- --
tI2KLKV 20 + 0.1 x CB tI2KHKL CI IIN 0 -- --
Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. C B = capacitance of one bus line in pF. 3. For information on the digital filter used, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
15.2
I2C AC Electrical Specifications
Table 44. I2C AC Electrical Specifications
Table 44 provides the AC timing parameters for the I2C interface.
All values refer to VIH (min) and V IL (max) levels (see Table 43).
Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: I2C bus devices Fall time of both SDA and SCL signals5
Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL
Min 0 1.3 0.6 0.6 0.6 100 -- 02
Max 400 -- -- -- -- -- -- 0.9 3 300
Unit kHz s s s s ns s
tI2CF
--
ns
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 56 Freescale Semiconductor
I2C
Table 44. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and V IL (max) levels (see Table 43).
Parameter Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis)
Symbol1 tI2PVKH tI2KHDX VNL VNH
Min 0.6 1.3 0.1 x NVDD 0.2 x NVDD
Max -- -- -- --
Unit s s V V
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DXKL has only to be met if the device does not stretch the low period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. 5. The device does not follow the I2C-BUS Specifications, Version 2.1, regarding the tI2CF AC parameter.
Figure 45 provides the AC test load for the I2C.
Output Z0 = 50 RL = 50 NVDD/2
Figure 45. I2C AC Test Load
Figure 46 shows the AC timing diagram for the I2C bus.
SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF
Figure 46. I2C Bus AC Timing Diagram
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 57
Timers
16 Timers
This section describes the DC and AC electrical specifications for the timers.
16.1
Timers DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the MPC8308 timers pins, including TIN, TOUT, and TGATE.
Table 45. Timers DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA -- -- 0 V VIN NVDD Min 2.4 -- -- 2.1 -0.3 -- Max -- 0.5 0.4 NVDD + 0.3 0.8 5 Unit V V V V V A
16.2
Timers AC Timing Specifications
Table 46. Timers Input AC Timing Specifications
Characteristic Symbol1 tTIWID Min 20 Unit ns
Table 46 provides the Timers input and output AC timing specifications.
Timers inputs--minimum pulse width
Notes: 1. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation
Figure 47 provides the AC test load for the Timers.
Output Z0 = 50 RL = 50 NVDD/2
Figure 47. Timers AC Test Load
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 58 Freescale Semiconductor
GPIO
17 GPIO
This section describes the DC and AC electrical specifications for the GPIO of MPC8308
17.1
GPIO DC Electrical Characteristics
Table 47. GPIO DC Electrical Characteristic
Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA -- -- 0 V VIN NVDD Min 2.4 -- -- 2.1 -0.3 -- Max -- 0.5 0.4 NVDD + 0.3 0.8 5 Unit V V V V V A
Table 47 provides the DC electrical characteristics for the GPIO.
17.2
GPIO AC Timing Specifications
Table 48. GPIO Input AC Timing Specifications
Characteristic GPIO inputs--minimum pulse width Symbol1 tPIWID Min 20 Unit ns
Table 48 provides the GPIO input and output AC timing specifications.
Notes: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
Figure 48 provides the AC test load for the GPIO.
Output Z0 = 50 RL = 50 NVDD/2
Figure 48. GPIO AC Test Load
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 59
IPIC
18 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins.
18.1
IPIC DC Electrical Characteristics
Table 49. IPIC DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL Condition -- -- -- IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.1 -0.3 -- 2.4 -- -- Max NVDD + 0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
Table 49 provides the DC electrical characteristics for the external interrupt pins.
18.2
IPIC AC Timing Specifications
Table 50. IPIC Input AC Timing Specifications
Characteristic IPIC inputs--minimum pulse width Symbol1 tPIWID Min 20 Unit ns
Table 50 provides the IPIC input and output AC timing specifications.
Notes: 1. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode.
19 SPI
This section describes the DC and AC electrical specifications for the SPI of the device.
19.1
SPI DC Electrical Characteristics
Table 51. SPI DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Symbol VIH VIL IIN Condition -- -- 0 V VIN NVDD Min 2.1 -0.3 -- Max NVDD + 0.3 0.8 5 Unit V V A
Table 51 provides the DC electrical characteristics for the MPC8308 SPI.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 60 Freescale Semiconductor
SPI
Table 51. SPI DC Electrical Characteristics (continued)
Characteristic Output high voltage Output low voltage Output low voltage Symbol VOH VOL VOL Condition IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.4 -- -- Max -- 0.5 0.4 Unit V V V
19.2
SPI AC Timing Specifications
Table 52. SPI AC Timing Specifications 1
Characteristic Symbol 2 tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH tNIIXKH tNEIVKH tNEIXKH 2 6 0 4 2 Min -- 0.5 Max 6 -- 8.5 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns
Table 52 provides the SPI input and output AC timing specifications.
SPI outputs valid--master mode (internal clock) delay SPI outputs hold--master mode (internal clock) delay SPI outputs valid--slave mode (external clock) delay SPI outputs hold--slave mode (external clock) delay SPI inputs--master mode (internal clock) input setup time SPI inputs--master mode (internal clock) input hold time SPI inputs--slave mode (external clock) input setup time SPI inputs--slave mode (external clock) input hold time
Notes: 1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Figure 49 provides the AC test load for the SPI.
Output Z0 = 50 RL = 50 NVDD/2
Figure 49. SPI AC Test Load
Figure 50 and Figure 51 represent the AC timing from Table 52. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 61
Package and Pin Listings
Figure 50 shows the SPI timing in slave mode (external clock).
SPICLK (input) tNEIVKH tNEIXKH
Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note)
tNEKHOV
Note: The clock edge is selectable on SPI.
Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 51 shows the SPI timing in master mode (internal clock).
SPICLK (output) tNIIVKH tNIIXKH
Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note)
tNIKHOV
Note: The clock edge is selectable on SPI.
Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram
20 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in a Moulded Array Process Ball Grid Array (MAPBGA). For information on the MAPBGA, see Section 20.1, "Package Parameters for the MPC8308 MAPBGA," and Section 20.2, "Mechanical Dimensions of the MPC8308 MAPBGA."
20.1
Package Parameters for the MPC8308 MAPBGA
The package parameters are as provided in the following list. The package type is 19 mm x 19 mm, 473 MAPBGA. Package outline 19 mm x 19 mm Interconnects 473 Pitch 0.80 mm Module height (typical) 1.39 mm Solder Balls 96.5 Sn/ 3.5Ag Ball diameter (typical) 0.40 mm
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 62 Freescale Semiconductor
Package and Pin Listings
20.2
Mechanical Dimensions of the MPC8308 MAPBGA
Figure 52 shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package.
Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG
Notes: 1. All dimensions are in millimeters. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 63
Package and Pin Listings
2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
20.3
Pinout Listings
Table 53. MPC8308 Pinout Listing
Signal Package Pin Number DDR Memory Controller Interface Pin Type Power Supply Notes
Table 53 provides the pin-out listing for the MPC8308, MAPBGA package.
MEMC_MDQ[0] MEMC_MDQ[1] MEMC_MDQ[2] MEMC_MDQ[3] MEMC_MDQ[4] MEMC_MDQ[5] MEMC_MDQ[6] MEMC_MDQ[7] MEMC_MDQ[8] MEMC_MDQ[9] MEMC_MDQ[10] MEMC_MDQ[11] MEMC_MDQ[12] MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26]
V6 Y4 AB3 AA3 AA2 AA1 W4 Y2 W3 W1 Y1 W2 U4 U3 V4 U6 T3 T2 R4 R3 P4 N6 P2 P1 N4 N3 N2
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDA GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 64 Freescale Semiconductor
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal MEMC_MDQ[27] MEMC_MDQ[28] MEMC_MDQ[29] MEMC_MDQ[30] MEMC_MDQ[31] MEMC_MDM[0] MEMC_MDM[1] MEMC_MDM[2] MEMC_MDM[3] MEMC_MDM[8] MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MDQS[8] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MWE MEMC_MRAS Package Pin Number M6 M2 M3 L2 L3 AB2 V3 P3 M7 K2 AC3 V1 R1 M1 K1 C3 B2 H4 C2 D2 D3 D4 E4 F4 E2 E1 F2 F3 C1 F7 G2 G3 D5 B4 Pin Type I/O I/O I/O I/O I/O O O O O O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O Power Supply GVDDB GVDDB GVDDB GVDDB GVDDB GVDDA GVDDA GVDDB GVDDB GVDDB GVDDA GVDDA GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 65
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal MEMC_MCAS MEMC_MCS[0] MEMC_MCS[1] MEMC_MCKE MEMC_MCK [0] MEMC_MCK [1] MEMC_MCK [2] MEMC_MCK [0] MEMC_MCK [1] MEMC_MCK [2] MEMC_MODT[0] MEMC_MODT[1] MEMC_MECC[0] MEMC_MECC[1] MEMC_MECC[2] MEMC_MECC[3] MEMC_MECC[4] MEMC_MECC[5] MEMC_MECC[6] MEMC_MECC[7] MVREF Package Pin Number C5 B6 C6 H3 A3 U2 G1 A4 U1 H1 A5 B5 L4 L6 K4 K3 J2 K6 J3 J6 G6 Local Bus Controller Interface LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 U18 V18 U16 Y20 AA21 AC22 V17 AB21 Y19 AA20 Y17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K 8 8 8 8 8 8 8 8 8 8 8 Pin Type O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I Power Supply GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB GVDDB Notes -- -- -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 66 Freescale Semiconductor
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal LD11 LD12 LD13 LD14 LD15 LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LCS[0] LCS[1] LCS[2] Package Pin Number AC21 AB20 V16 AA19 AC17 AC20 Y16 U15 V15 AA18 AA17 AC19 AA16 AB18 AC18 V14 AB17 AA15 AC16 Y14 AC15 U13 V13 Y13 AB15 AA14 AB14 U12 V12 Y12 AC14 AA13 AB13 AA12 Pin Type I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Power Supply NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K Notes 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 4 4
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 67
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal LCS[3] LWE[0] /LFWE0/LBS0 LWE[1]/LBS1 LBCTL LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE/LFRE LGPL3/LFWP LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK0 DUART UART_SOUT1/MSRCID0/LSRCID0 UART_SIN1/MSRCID1/LSRCID1 UART_SOUT2/MSRCID2/LSRCID2 UART_SIN2/MSRCID3/LSRCID3 PEX PHY TXA TXA RXA RXA SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SD_PLL_TPA_ANA SDAVDD_0 SDAVSS_0 I2C interface IIC_SDA1 IIC_SCL1 C9 A9 I/O I/O NVDDA NVDDA 2 2 C14 C15 A13 B13 A15 C12 D12 F13 A11 F11 G12 F12 O O I I I I I O I O I I XPADVDD XPADVDD XCOREVDD XCOREVDD XCOREVDD XCOREVDD XCOREVDD -- XPADVDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C17 B18 D17 D18 O I/O O I/O NVDDB NVDDB NVDDB NVDDB -- -- -- -- Package Pin Number Y11 AB11 AC11 U11 Y10 AA10 AB10 AC10 AB9 Y9 AC12 Pin Type O O O O O O O O I/O O O Power Supply NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K Notes 4 -- -- -- -- -- 4 -- 4 -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 68 Freescale Semiconductor
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal IIC_SDA2/CKSTOP_OUT IIC_SCL2/CKSTOP_IN Interrupts IRQ[0]/MCP_IN IRQ[1]/MCP_OUT IRQ[2] /CKSTOP_OUT IRQ[3] /CKSTOP_IN JTAG TCK TDI TDO TMS TRST TEST TEST_MODE System Control HRESET PORESET SRESET Clocks SYS_CLK_IN RTC_PIT_CLOCK MISC QUIESCE THERM0 ETSEC1 TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RXD[3] B20 B21 F18 A22 D21 C22 I I O I I I NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC -- -- 3 -- -- -- AA7 AC7 O I NVDDP_K NVDDP_K -- 6 AC8 AA23 I I NVDDP_K NVDDJ -- -- AA9 AA8 AB7 I/O I I/O NVDDP_K NVDDP_K NVDDP_K 1 -- -- AC6 I NVDDP_K 5 Y7 U9 AC5 AA6 V8 I I O I I NVDDP_K NVDDP_K NVDDP_K NVDDP_K NVDDP_K -- 4 3 4 4 A17 F16 B17 A18 I I/O I/O I NVDDB NVDDB NVDDB NVDDB -- -- -- -- Package Pin Number D10 C10 Pin Type I/O I/O Power Supply NVDDA NVDDA Notes 2 2
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 69
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal TSEC1_RXD[2] TSEC1_RXD[1] TSEC1_RXD[0] TSEC1_RX_ER TSEC1_TX_CLK/TSEC1_GTX_CLK125 TSEC1_TXD[3]/CFG_RESET_SOURCE[0] TSEC1_TXD[2]/CFG_RESET_SOURCE[1] TSEC1_TXD[1]/CFG_RESET_SOURCE[2] TSEC1_TXD[0]/CFG_RESET_SOURCE[3] TSEC1_TX_EN/LBC_PM_REF_10 TSEC1_TX_ER/LB_POR_CFG_BOOT_ECC Ethernet Mgmt TSEC1_MDC TSEC1_MDIO eSDHC/GTM SD_CLK/GPIO_16 SD_CMD/GPIO_17 SD_CD/GTM1_TIN1/GPIO_18 SD_WP/GTM1_TGATE1/GPIO_19 SD_DAT[0]/GTM1_TOUT1/GPIO_20 SD_DAT[1]/GTM1_TOUT2/GPIO_21 SD_DAT[2]/GTM1_TIN2/GPIO_22 SD_DAT[3]/GTM1_TGATE2/GPIO_23 SPI SPIMOSI/MSRCID4/LSRCID4 SPIMISO/MDVAL/LDVAL SPICLK SPISEL GPIO/ETSEC2 GPIO[0]/TSEC2_COL GPIO[1]/TSEC2_TX_ER GPIO[2]/TSEC2_GTX_CLK GPIO[3]/TSEC2_RX_CLK G21 K23 H18 G23 I/O I/O I/O I/O NVDDF NVDDF NVDDF NVDDF -- -- -- -- AB5 Y6 AA5 AB4 I/O I/O I/O I NVDDP_K NVDDP_K NVDDP_K NVDDP_K -- -- -- -- D7 G9 A7 D8 C8 B8 A8 B9 O I/O I I I/O I/O I/O I/O NVDDA NVDDA NVDDA NVDDA NVDDA NVDDA NVDDA NVDDA -- -- -- -- -- -- -- -- A20 C19 O I/O NVDDB NVDDB -- 2 Package Pin Number C21 C20 D20 C23 E23 F22 F21 E21 D22 F20 E22 Pin Type I I I I I I/O I/O I/O I/O O I/O Power Supply NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC NVDDC Notes -- -- -- -- -- -- -- -- -- -- 7
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 70 Freescale Semiconductor
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal GPIO[4]/TSEC2_RX_DV GPIO[5]/TSEC2_RXD3 GPIO[6]/TSEC2_RXD2 GPIO[7]/TSEC2_RXD1 GPIO[8]/TSEC2_RXD0 GPIO[9]/TSEC2_RX_ER GPIO[10]/TSEC2_TX_CLK/TSEC2_GTX_CLK125 GPIO[11]/TSEC2_TXD3 GPIO[12]/TSEC2_TXD2 GPIO[13]/TSEC2_TXD1 GPIO[14]/TSEC2_TXD0 GPIO[15]/TSEC2_TX_EN Package Pin Number J18 J20 H22 H21 H20 J21 J23 K22 K20 K18 J17 K21 USB/IEEE1588/GTM USBDR_PWR_FAULT USBDR_CLK USBDR_DIR USBDR_NXT USBDR_TXDRXD0 USBDR_TXDRXD1 USBDR_TXDRXD2 USBDR_TXDRXD3 USBDR_TXDRXD4 USBDR_TXDRXD5 USBDR_TXDRXD6 USBDR_TXDRXD7 USBDR_PCTL0 USBDR_PCTL1 USBDR_STP TSEC_TMR_CLK/ GPIO[8] GTM1_TOUT3/ GPIO[9] GTM1_TOUT4/ GPIO[10] TSEC_TMR_TRIG1/ GPIO[11] TSEC_TMR_TRIG2/ GPIO[12] TSEC_TMR_GCLK P20 R23 R21 P18 T22 T21 U23 U22 T20 R18 V23 V22 R17 U20 V21 W23 T18 V20 W21 Y21 L17 I I I I I/O I/O I/O I/O I/O I/O I/O I/O O O O I O O I I O NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDH NVDDG -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF NVDDF Notes -- -- -- -- -- -- -- -- -- -- -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 71
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal TSEC_TMR_PP1 TSEC_TMR_PP2 TSEC_TMR_PP3/ GPIO[13] TSEC_TMR_ALARM1 TSEC_TMR_ALARM2/ GPIO[14] GPIO[7] TSEC2_CRS TSEC2_TMR_RX_ESFD/ GPIO[1] TSEC2_TMR_TX_ESFD/GPIO[2] TSEC1_TMR_RX_ESFD/GPIO[3] TSEC1_TMR_TX_ESFD/ GPIO[4] GTM1_TGATE3 GTM1_TIN4 GTM1_TGATE4/ GPIO[15] GTM1_TIN3 GPIO[5] GPIO[6] Package Pin Number L18 L21 L22 L23 M23 M22 M21 M18 M20 N23 N21 N20 N18 P23 P22 N17 P21 Power and Ground Supplies AVDD1 AVDD2 NC, No Connection VDD R6 V10 Y23, B11, B16, D16 H8, H9, H10, H14, H15, H16, J8, J16, K8, K16, L8, L16, M8, M16, N8, N16, P8, P16, R8, R16, T8, T9, T10, T11, T12, T13, T14, T15, T16 I I -- I -- -- -- -- -- -- -- -- Pin Type O O O O O O O O O O O I I I I I I Power Supply NVDDG NVDDG NVDDG NVDDG NVDDG -- NVDDG NVDDG NVDDG NVDDG NVDDG NVDDG NVDDG NVDDG NVDDG NVDDH NVDDH Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 72 Freescale Semiconductor
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal VSS Package Pin Number A2, A21, B1, B19, B23, C4, C16, D6, D19, E3, F8, F15, F17, F23, G7, G8, G10, G15, G16, G17, G20, H2, H6, H7, H17, H23, J7, J9, J10, J11, J12, J13, J14, J15, K9, K10, K11, K12, K13, K14, K15, L1, L7, L9, L10, L11, L12, L13, L14, L15, L20, M4, M9, M10, M11, M12, M13, M14, M15, N9, N10, N11, N12, N13, N14, N15, P6, P7, P9, P10, P11, P12, P13, P14, P15, R2, R7, R9, R10, R11, R12, R13, R14, R15, R22, T6, T7, U8, U17, U21, V2, V7, V9, V11, W20, Y8, Y15, AA4, AB1, AB6, AB12, AB19, AC2, AC9, AC23 B7, B10, C7, D9, F9 A16, A19, C18 A23, B22, D23, E20, G18 G22, J22, K17 M17, N22 P17, R20, T17, T23, W22, Y22 AB23, AA22 U10, U14, Y5, Y18, AA11, AB8, AB16, AB22, AC4, AC13 A1, A6, B3, D1, F1, F6, G4, J1, J4, K7, N1, N7, T1, T4, U7, Y3, AC1 D15, F10, F14 A10, B15, D14, G13, G14, H12 Pin Type I Power Supply -- Notes --
NVDDA NVDDB NVDDC NVDDF NVDDG NVDDH NVDDJ NVDDP_K
I I I I I I I I
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
GVDD
I
--
--
XPADVDD XPADVSS
I I
-- --
-- --
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 73
Package and Pin Listings
Table 53. MPC8308 Pinout Listing (continued)
Signal XCOREVDD XCOREVSS Package Pin Number A14, B12, C13 A12, B14, C11, D11, D13, G11, H11, H13 Pin Type I I Power Supply -- -- Notes -- --
Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 k) should be placed on this pin to NVDD 2. This pin is an open drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to NV DD. 3. This output is actively driven during reset rather than being three-stated during reset. 4. This pin has weak internal pull-up that is always enabled. 5. This pin must always be tied to VSS. 6. Internal thermally sensitive resistor, resistor value varies linearly with temperature. Useful for determining the junction temperature. 7. The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables the ECC by default. To disable the ECC an external strong pull up resistor or a buffer released to high impedance is needed. 8. This pin has weak internal pull-down that is always enabled
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 74 Freescale Semiconductor
Clocking
21 Clocking
Figure 53 shows the internal distribution of clocks within the device.
MPC8308
e300 Core
x M1
e300 PLL csb_clk
clk tree
x L2
System PLL ref 24-66 MHz SYS_CLK_IN fb
Clk Gen
ddr_clk lbc_clk
DDR Clock Divider /2 /n LBC Clock Divider
MCK[0:2] MCK[0:2] DDR Memory Device
Local Bus Memory Device
SD_CLK
eSHDC
PCI Express Protocol Converter eTSEC1 TSEC1_RX_CLK
PCVTR Mux SD_REF_CLK SD_REF_CLK_B 125/100 MHz
1 2
+ -
PLL
SerDes PHY
TSEC1_TX_CLK/ TSEC1_GTX_CLK125
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].
Figure 53. MPC8308 Clock Subsystem
The following external clock sources are utilized on the MPC8308: * System clock (SYS_CLK_IN) * Ethernet Clock (TSEC1_RX_CLK/TSEC1_TX_CLK/TSEC1_GTX_CLK125 for eTSEC) * SerDes PHY clock * eSHDC clock (SD_CLK) For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual. All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other source that provides a standard CMOS square wave input.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 75
Clocking
21.1
System Clock Domains
The primary clock input (SYS_CLK_IN) frequency is multiplied up by the system phase-locked loop (PLL) and the clock unit to create three major clock domains: * The coherent system bus clock (csb_clk) * The internal clock for the DDR controller (ddr_clk) * The internal clock for the local bus interface unit (lbc_clk) The csb_clk frequency is derived as follows: csb_clk = [SYS_CLK_IN] x SPMF The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual. The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (/2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK0:2). The LBC clock divider ratio is controlled by LCCR[CLKDIV]. For more information, see the Reset Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual. In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. These units have a default clock ratio that can be configured by a memory-mapped register after the device comes out of reset. Table 54 specifies which units have a configurable clock frequency. For more information, see Reset Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual.
Table 54. Configurable Clock Units
Unit eTSEC1,eTSEC2 I2C DMA complex PCIEXP eSDHC USB Default Frequency Options Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk,csb_clk/2, csb_clk/3 Off, csb_clk,csb_clk/2,csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3
csb_clk/3 csb_clk csb_clk csb_clk csb_clk csb_clk
NOTE The clock ratios of these units must be set before they are accessed.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 76 Freescale Semiconductor
Clocking
Table 55 provides the operating frequencies for the device under recommended operating conditions (Table 2).
Table 55. Operating Frequencies for MPC8308
Characteristic1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) DDR2 memory bus frequency (MCK)2 Local bus frequency (LCLK0)3 Maximum Operating Frequency 400 133 133 66 Unit MHz MHz MHz MHz
Notes: 1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCK, LCLK0, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The DDR data rate is 2x the DDR memory bus frequency. 3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x the csb_clk frequency (depending on RCWL[LBCM]).
21.2
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 56 shows the multiplication factor encodings for the system PLL.
Table 56. System PLL Ratio
RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110-1111 csb_clk : SYS_CLK_IN Reserved Reserved 2:1 3:1 4:1 5:1 Reserved
As described in Section 21, "Clocking," the LBCM, DDRCM, and SPMF parameters in the reset configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 77
Clocking
coherent system bus clock (csb_clk). Table 57 shows the expected frequency values for the CSB frequency for select csb_clk to SYS_CLK_IN ratios.
Table 57. CSB Frequency Options
Input Clock Frequency (MHz) SPMF csb_clk :Input Clock Ratio 25 0010 0100 0101 2:1 4:1 5:1 125 133 33.33 66.67 133
21.3
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 58 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 58 should be considered as reserved. NOTE Core VCO frequency = core frequency x VCO divider. The VCO divider, which is determined by RCWLR[COREPLL], must be set properly so that the core VCO frequency is in the range of 400-800 MHz.
Table 58. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk: csb_clk Ratio1
0-1 2-5 0000 6 0 n 0 0 0 1 1 1 0 0 0 1 1 PLL bypassed (PLL off, csb_clk clocks core directly) n/a 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2.5:1 2.5:1
VCO Divider (VCOD)2
nn
11 00 01 10 00 01 10 00 01 10 00 01
PLL bypassed (PLL off, csb_clk clocks core directly) n/a 2 4 8 2 4 8 2 4 8 2 4
nnnn
0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 78 Freescale Semiconductor
Thermal
Table 58. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk: csb_clk Ratio1
0-1 10 00 01 10 Notes:
1 2
VCO Divider (VCOD)2
2-5 0010 0011 0011 0011
6 1 0 0 0 2.5:1 3:1 3:1 3:1 8 2 4 8
For any core_clk:csb_clk ratios, the core_clk must not exceed its maximum operating frequency of 333 MHz. Core VCO frequency = core frequency x VCO divider. Note that VCO divider has to be set properly so that the core VCO frequency is in the range of 400-800 MHz.
22 Thermal
This section describes the thermal specifications of the device.
22.1
Thermal Characteristics
Table 59. Package Thermal Characteristics for MAPBGA
Characteristic Board Type Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- -- Natural Convection Symbol Value 42 27 35 24 17 9 2 Unit C/W C/W C/W C/W C/W C/W C/W Notes 1,2 1,2,3 1,3 1,3 4 5 6
Table 59 provides the package thermal characteristics for the 473, 19 x 19 mm MAPBGA.
Junction to Ambient Natural Convection Junction to Ambient Natural Convection Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board Junction to Case Junction to Package Top
RJA RJA RJMA RJMA RJB RJC JT
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 79
Thermal
Table 59. Package Thermal Characteristics for MAPBGA (continued)
Characteristic Board Type Symbol Value Unit Notes
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
22.2
Thermal Management Information
For the following sections, PD = (VDD x IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers.
22.2.1
Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single-layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible.
22.2.2
Estimation of Junction Temperature with Junction-to-Board Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 80 Freescale Semiconductor
System Design Information
the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (C) TB = board temperature at the package perimeter (C) RJB = junction-to-board thermal resistance (C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
22.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TJ = junction temperature (C) TT = thermocouple temperature on top of package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
23 System Design Information
This section provides electrical and thermal design recommendations for successful application of the device
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 81
System Design Information
23.1
System Clocking
The device includes two PLLs. 1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input. The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio configuration bits as described in Section 21.2, "System PLL Configuration." 2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 21.3, "Core PLL Configuration."
23.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 for core PLL and AVDD2 for the platform PLL). The AVDD level should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a low-pass filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits as illustrated in Figure 54, one to each of the two AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs' resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV DD pin, which is on the periphery of package, without the inductance of vias. Figure 54 shows the PLL power supply filter circuits.
10 V DD 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD1 and AVDD2
Figure 54. PLL Power Supply Filter Circuit
23.3
Decoupling Recommendations
Due to large address and data buses and high-operating frequencies, the device can generate transient power surges and high-frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pin of the device.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 82 Freescale Semiconductor
System Design Information
These decoupling capacitors should receive their power from separate VDD, NVDD, GVDD, LVDD, and VSS power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, NVDD, GVDD, LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are in the range of 100-330 F (AVX TPS tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values and types of bulk capacitors.
23.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to NVDD, GVDD, and LVDD as required. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, NVDD, AVDD1, AVDD2, GVDD, LVDD, and VSS pins of the device.
23.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C, MDIO, and HRESET). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD or VSS. Then, the value of each resistor is varied until the pad voltage is NVDD/2 (Figure 55). The output impedance is the average of two components: the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 83
System Design Information
NVDD
RN
SW2 Data Pad SW1
RP
VSS
Figure 55. Driver Impedance Measurement
The value of this resistance and the strength of the driver's current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource x Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value R term. The measured voltage is V2 = (1/(1/R1 + 1/R2)) x Isource. Solving for the output impedance gives Rsource = Rterm x (V1/V2 - 1). The drive current is then Isource = V1/Rsource. Table 60 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal NVDD, 105C.
Table 60. Impedance Characteristics
Impedance RN RP Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target DDR DRAM 20 Target 20 Target Symbol Z0 Z0 Unit
Note: Nominal supply voltages. See Table 2, T j = 105C.
23.6
Configuration Pin Muxing
The device provides the user with power-on configuration options that can be set through the use of external pull-up or pull-down resistors of 4.7 K on certain output pins (see customer-visible configuration pins). These pins are generally used as output-only pins in normal operation. While PORESET is asserted, these pins are treated as inputs. The value presented on these pins while PORESET is asserted is latched when PORESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 84 Freescale Semiconductor
Ordering Information
23.7
Pull-Up Resistor Requirements
The device requires high-resistance pull-up resistors (10 k is recommended) on open drain type pins including I2C, Ethernet management MDIO, HRESET and IPIC (integrated programmable interrupt controller). Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions, because most have asynchronous behavior and spurious assertion that give unpredictable results.
24 Ordering Information
This section presents ordering information for the devices discussed in this document, and it shows an example of how the parts are marked. Ordering information for the devices fully covered by this document is provided in Section 24.1, "Part Numbers Fully Addressed by This Document."
24.1
Part Numbers Fully Addressed by This Document
Table 61 provides the Freescale part numbering nomenclature for the MPC8308 family. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the maximum processor core frequency, the part numbering scheme also includes the maximum effective DDR memory speed. Each part number also contains a revision code which refers to the die mask revision number.
Table 61. Part Numbering Nomenclature
MPC
Product Code MPC
nnnn
Part Identifier 8308
C
Temperature Range1 Blank = 0 to 105C C = -40 to 105C
VM
Package2 VM = Pb-free 473 MAPBGA
AD
e300 Core Frequency3 AD = 266 MHz AF = 333 MHz AG = 400MHz
D
DDR Frequency D = 266 MHz
A
Revision Level Contact local Freescale sales office
Notes: 1. Contact local Freescale office on availability of parts with C temperature range. 2. See Section 20, "Package and Pin Listings," for more information on available package types. 3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies.
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 85
Document Revision History
24.2
Part Marking
Parts are marked as in the example shown in Figure 56.
MPCnnnnCVMADDA core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ
PBGA Notes: ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code.
Figure 56. Freescale Part Marking for PBGA Devices
Table 62 shows the SVR settings.
Table 62. SVR Settings
Device MPC8308 Package MAPBGA SVR 0x8101 _0110
Note: PVR = 8085_0020 for the device.
25 Document Revision History
Table 63 provides a revision history for this hardware specification.
Table 63. Document Revision History
Revision Rev 1 Date 07/2010 Substantive Change(s) * In "Table 4," TA = 105 replaced with TJ = 105 * In "Table 8," fSYS_CLK_IN (Max) = 66 replaced with 66.67 and tSYS_CLK_IN (Min) = 15.15 replaced with 15 * In "Table 53," TSEC1_TMR_RX_ESFD replaced with TSEC2_TMR_RX_ESFD TSEC1_TMR_TX_ESFD replaced with TSEC2_TMR_TX_ESFD TSEC0_TMR_RX_ESFD replaced with TSEC1_TMR_RX_ESFD TSEC0_TMR_TX_ESFD replaced with TSEC1_TMR_TX_ESFD * In "Table 56," rows from 1000 to 1111 removed Initial release
Rev 0
05/2010
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 86 Freescale Semiconductor
Document Revision History
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 Freescale Semiconductor 87
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Document Number: MPC8308EC Rev. 1 07/2010

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